Chip Structure

  • Base Layer : P-TEOS*
  • Metal Layer : TiW / AI-1.0%Si-0.5%Cu
  • Passivation Layer : P-TEOS* / P-SiN

*TEOS : Tetraethoxysilane



Wafer Size 6 inch
Chip Size 15.1mm×1.6mm
Pad pitch 30μm
Function Daisy Chain
Pad config Peripheral
Bump material(process) Gold(plating) , Cu
Pad Size 28μm×120μm
Passivation opening 6μm×80μm
UBM Size 20μm×100μm
Bump Size 20μm×100μm
Scribe width 100μm
Number of Pad 726 pad/chip
Number of Chip 530 chip/wafer

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In the News

Practical Components to Exhibit at the IPC High Reliability Forum
Practical is announcing that it will display its latest technology at the upcoming IPC High Reliability Forum and exhibition scheduled to take place May 15-17, 2018 in ... [read more]

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