Chip Structure

  • Base Layer : P-TEOS*
  • Metal Layer : TiN / AI-0.5%Cu
  • Passivation Layer : HDP* / P-SiN

*TEOS : Tetraethoxysilane
*HDP : High Density Plasma



Wafer Size 8 inch
Wafer Thickness 725±25μm
Chip Size 7.3mm ♦
Pad Pitch 60μm
Function Daisy Chain
Bump Size -
Bump Height -
Number of Pad 488 pads/chip
Number of Chip 478 chips/wafer
Polyimide (Option) O
Evaluation KIT -
  ♦ Bottom Side

IPC Validation Services

New Product

.4mm Pitch eWLP Dummy Wafer-Amkor
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In the News

Practical Components to Exhibit at the IPC High Reliability Forum
Practical is announcing that it will display its latest technology at the upcoming IPC High Reliability Forum and exhibition scheduled to take place May 15-17, 2018 in ... [read more]

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