TEG WM40-0103JY

Practical Components -TEG WM40-0103JY


Chip Structure


  • Base Layer : P-TEOS
  • Metal layer : TiN / Al-0.5%Cu
  • Passivation Layer : HDP / P-SiN

*TEOS : Tetraethoxysilane


Wafer Size 8 inch
Wafer Thickness 725±25μm
Chip Size 10.00mm x 8.00mm

Daisy Chain

Pad Size 35μm
Passivation Operation φ10um (Octagon)
Number of Pad

I/O area : 40um pitch x 1200 pad
Dummy area : 300um pitch x 714 pad

Electrode Cu Pillar
Bump Size φ20μm
Bump Pitch

1. 40μm
2. 300μm

Bump Height


Number of Chip

312 chips/wafer

IPC Validation Services

New Product

.4mm Pitch eWLP Dummy Wafer-Amkor
.4mm Pitch eWLP Dummy Wafer-Amkor


Technical Center

In the News

Practical Components to Exhibit at the IPC High Reliability Forum
Practical is announcing that it will display its latest technology at the upcoming IPC High Reliability Forum and exhibition scheduled to take place May 15-17, 2018 in ... [read more]

Request Catalog


Request or download our catalog and sign-up for our newsletter.